A typical dynamic random access memory (DRAM) cell includes a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor. The MOSFET is used as a pass transistor to allow charge to be transferred to and from a capacitor used to store data.
A DRAM cell using a junction field effect transistor having a buried gate used to store charge is disclosed in Heald et al., “Multilevel Random-Access Memory Using One Transistor Per Cell,” IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, pp. 519-528, August 1979, the contents of which are incorporated herein. The buried gate in Heald et al. is a n-type diffusion buried inside a p-type region so that the buried gate is surrounded on all sides by the p-type region. Such a structure can require an implant mask during the formation of the n-type buried gate. Such a mask may need proper alignment, particularly as minimum dimensions of the DRAM become deep sub-micron.